1. Field of the Invention
This invention relates generally to synchronization circuits and, more particularly, to an MOS three-state output buffer synchronized with more than a single clock signal.
2. Description of the Prior Art
The advantages offered by NMOS technology are well known; e.g. higher density, greater yield, etc. The smaller NMOS device geometries permit a greater number of devices to be produced per unit area or, stated another way, a single device will occupy less space. This characteristic is extremely important in the design and fabrication of complex digital integrated circuits; for example, single chip microprocessors. However, if progress is to continue, further improvements in density, yield, speed and power consumption must be achieved.
In complex digital circuitry, it is often necessary to receive an input signal which is not necessarily synchronized with the clock signal which controls the digital circuitry. Such circuits are well known. However, in order to improve speed and flexibility of the overall system, it would be desirable to synchronize the incoming signal with more than a single rigid clock signal. Further, to enhance flexibility, it would be desirable to provide a synchronization circuit, which is capable of operating in a three-state mode such that upon receipt of an appropriate command, the output is left floating and available for use by other circuitry. Flexibility can be further enhanced by providing an output buffer which may be made conditional; that is, permit the buffer to discharge only when an external data signal commands it.